Power-Aware Recursive Squarer Architecture| #ApproximateComputing #DigitalCircuits #LowPowerDesign #VLSIDesign #HardwareOptimization

1. Introduction

In the era of compact, high-performance, and energy-efficient digital systems, traditional arithmetic circuits face challenges due to their high resource requirements. Squaring operations, which are commonly used in signal processing, image analysis, and machine learning, often consume significant area and power. This work explores a hardware-efficient approach using approximate computing and recursive squaring techniques to reduce complexity while maintaining acceptable levels of computational accuracy.


2. Approximate Computing in Arithmetic Circuits

Approximate computing is a design strategy that allows small, controlled inaccuracies in arithmetic operations to reduce hardware overhead. This paradigm is well-suited for error-resilient applications like multimedia processing, where perfect precision is not critical. By leveraging approximate logic, designers can achieve significant savings in power, area, and delay.

3. Recursive Squaring Methodology

Recursive squaring is a divide-and-conquer technique that breaks down a large squaring operation (e.g., 8-bit input) into smaller components. It simplifies the overall computation by reusing partial results and reducing the number of operations. This makes it an ideal structure for integrating 4-bit approximate squarers and achieving further optimization.

4. Proposed 4-Bit Approximate Squarers (P1–P4)

Four new 4-bit approximate squarers—P1, P2, P3, and P4—have been designed by simplifying an exact squarer and modifying internal logic based on Karnaugh map analysis and truth table reduction. Each version introduces a different level of approximation, optimizing hardware use in unique ways:

  • P1: Simplifies mid-bit computations by allowing overestimation in selected cases.

  • P2: Removes the most significant term to reduce complexity.

  • P3: Uses signal approximation via Karnaugh map to eliminate gates.

  • P4: Combines multiple simplification strategies for the best trade-off.

5. Hardware Implementation and Results

The squarers were implemented and synthesized using Cadence Genus with a 45nm technology library. Simulation and analysis revealed substantial improvements over exact squarers:

  • Area savings: Up to 92.59%

  • Power reduction: Up to 50.20%

  • Delay improvement: Up to 57.53%

These optimizations were achieved while maintaining controlled error margins suitable for real-world applications.

6. Error Metrics and Analysis

To evaluate the trade-offs, several error metrics were used:

  • Error Rate (ER)

  • Mean Relative Error Distance (MRED)

  • Mean Normalized Error Distance (MNED)

These metrics show that the designs maintain output quality within acceptable thresholds, making them highly practical for use in error-tolerant environments.

7. Application Use Cases

The approximate squarers were tested in:

  • Image energy calculation – crucial for edge detection and enhancement tasks.

  • AM signal demodulation – used in communication systems.

In both cases, the circuits produced accurate-enough results with significantly reduced resource usage, proving their real-world applicability.

8. Conclusion

This work demonstrates how recursive squaring combined with approximate computing leads to highly efficient digital arithmetic circuits. The proposed 4-bit squarers—P1 through P4—offer flexible design choices for different accuracy and efficiency needs. Their application in image and signal processing proves that small compromises in precision can yield massive hardware benefits, aligning with the future of low-power, real-time, and embedded computing systems.

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